The present invention relates to semiconductor elements and a liquid crystal display apparatus. More particularly, the invention relates to an active matrix liquid crystal display apparatus of high image quality incorporating highly reliable thin film semiconductor elements.
There exist active matrix liquid crystal display apparatuses incorporating thin film transistors (TFTs) to display image and text information in combination with OA equipment. For researchers working on this type of liquid crystal display, attaining higher resolution and higher image quality than ever has been a crucial task in addition to the efforts at lowering fabrication costs. To meet the challenges requires improving the performance of TFTs, i.e., a key device of the liquid crystal display. An attempt to form high-performance TFTs on an inexpensive glass substrate is disclosed illustratively in IEEE Transaction on Electron Devices, 1989, Vol. 36, pp. 351-359. The disclosure involves using TFTs to constitute peripheral drivers for driving a TFT active matrix, the TFTs being integrated on a single substrate to reduce fabrication costs. If advanced peripheral drivers are integrated on a glass substrate, the structure of circuits to be mounted externally and their assembling processes will be more simplified, which will translate into substantially reduced mounting costs. To devise a high-performance circuit configuration requires adopting more advanced TFTs than ever before. Today, TFTs formed on a polysilicon film (poly-Si TFTs) are hailed for effective use in liquid crystal display apparatuses that integrate peripheral drivers. In order to form a liquid crystal display apparatus with integrated peripheral drivers on an inexpensive glass substrate, it is necessary to reduce to 350xc2x0 C. or lower the temperature of a process in which to form the TFTs. In such a low-temperature process, the quality of gate insulating films of the TFTs is not as high as that of thermal oxidation films fabricated at a higher temperature. The comparatively low quality of the TFTs can trigger deterioration of the elements attributable to the injection of hot carriers. In recent years, the mobility of carriers within TFTs has been improved since the introduction of high-quality polysilicon film fabrication technology using laser recrystallization. This has also drawn attention to the importance of viable solutions to the problem of element deterioration. Obviously, degraded TFT characteristics can directly affect the quality of image display; images can flicker or lose their contrast factor due to the concomitant deterioration in the characteristics of drivers or pixel switching elements.
The phenomenon of element deterioration attributable to hot carriers is known to be triggered by high electric fields near drain junctions of transistors. As ways to prevent such degradation, a number of structures have been proposed to attenuate the drain junction field in submicron-order transistors used in silicon LSIs. Illustratively, a dual diffusion drain (DDD) structure having arsenic (As) and phosphorus (P) diffused therein is discussed in IEEE Transaction on Electron Devices, 1983, Vol. 30, pp. 652-657. A lightly doped drain (LDD) structure is proposed in IEEE Transaction on Electron Devices, 1980, Vol. 27, pp. 1359-1367. The proposed LDD structure involves having a low-density impurity diffusion layer interposed between a channel segment and a drain diffusion layer. This structure has since gained widespread acceptance in LSI devices. Some adverse phenomena specific to the LDD structure are minimized by the so-called gate overlapped drain (GOLD) structure having low-density impurity diffusion layers and part of gate electrodes overlapping one another with insulating films interposed therebetween, as proposed in IEEE Transaction on Electron Devices, 1988, Vol. 35, pp. 2088-2093.
Meanwhile, higher levels of resolution and larger display screens of liquid crystal display apparatuses have created a serious problem: signal delays caused by finite wiring resistance and wiring capacity. A number of wiring structures using low-resistance materials such as aluminum (Al) and copper (Cu) have been proposed as solutions to that problem. Illustratively, Japanese Patent Laid-open No. Sho 64-35421 discloses a wiring structure having a metal subject to high anodic oxidation and a metal of high electrical conductivity stacked one upon another.
The GOLD structure is highly effective in improving the reliability of transistors by substantially reducing peak values of drain junction fields therein. As such, the GOLD structure is thought to be an effective way to enhance the reliability of polysilicon TFTs used in liquid crystal display apparatuses. One disadvantage of the GOLD structure is that its complicated element constitution necessitates installation of elaborate fabrication processes. This has proved to be a severe problem for liquid crystal display apparatuses because cost reduction is one of their top priorities. It is difficult to implement the proposed structure unmodified as has been applied to silicon LSIs so far.
It is therefore an object of the present invention to overcome the above and other deficiencies of the prior art and to provide a highly reliable TFT structure that may be formed with a minimum of additional fabrication processes. Another object of the present invention is to provide, in addition to the dependable TFTS, a low-resistance wiring structure suitable for a liquid crystal display apparatus having a wide, fine-resolution screen.
In carrying out the invention and according to one aspect thereof, there is provided a liquid crystal display apparatus comprising a pair of substrates, one of which has a plurality of scanning wires, a plurality of signal wires intersecting the scanning wires in a matrix fashion, and a plurality of semiconductor elements placed at intersection points between the scanning wires and the signal wires. Each of the plurality of semiconductor elements includes: a semiconductor layer having an intrinsic semiconductor region and a pair of semiconductor regions of a given conductivity type which sandwich the intrinsic semiconductor region and which are each made of a high-resistance region and a low-resistance region; a first electrode formed on the intrinsic semiconductor region with an insulating film interposed therebetween; and a second and a third electrode connected to the low-resistance regions of the pair of semiconductor regions of the given conductivity type. Each of the plurality of scanning wires constitutes the first electrode of the corresponding one of the plurality of semiconductor elements. The first electrode has first wiring formed on the insulating film and second wiring formed on the first wiring, part of the second wiring being overlaid on part of the high-resistance regions of the pair of semiconductor regions of the given conductivity type with the insulating film interposed therebetween.
In a preferred structure according to the invention, the second wiring may be formed so as to cover the first wiring. The second wiring may preferably be formed on sides of the first wiring. Ends of the second wiring may be tapered.
In a further preferred structure according to the invention, the low-resistance regions of the pair of semiconductor elements of the given conductivity type may be formed in self-aligned relation to the second wiring. With this structure, boundaries of the low-resistance regions which are viewed in perpendicular relation to the substrates may coincide with boundaries of the second wiring which are viewed in perpendicular relation to the substrates.
In yet another preferred structure according to the invention, the second wiring may be formed on the first wiring with an insulating film interposed therebetween. With this structure, the first and the second wiring may be connected via contact holes to ensure the same potential over the wiring.
According to the invention, the first electrode (gate electrode) of each semiconductor element (TFT) and the high-resistance semiconductor layer are arranged to overlap to form the so-called GOLD structure. This structure allow the resistance of the high-resistance semiconductor layer to be controlled (i.e., lowered) by the gate electrode. That in turn attenuates electrical fields in the high-resistance semiconductor layer to forestall element deterioration caused by the injection of hot carriers into an insulating film over the high-resistance semiconductor layer, a phenomenon specific to the LDD structure. Lowering the resistance of the high-resistance semiconductor layer prevents lessening, due to the presence of that layer, of the ability of the elements to drive currents. Such improvements combine to provide highly reliable TFTs offering an enhanced current driving capability.
A minimum process increase is required to implement the above structure: a process for forming and patterning the second wiring need only be added.
It is not mandatory to cover the first wiring with the second wiring as long as the second wiring is kept equal in potential to the first wiring. That is, the second wiring may be formed on the first wiring with an insulating film interposed therebetween. In this case, however, the first and the second wiring must be connected outside the elements.
When the first wiring is isolated from the second wiring by the insulating film, the two kinds of wiring may be arranged to constitute an additional capacity to retain electrical charges. If the thickness of a second insulating film is suitably reduced, the added capacity increases the capacity value per unit area while the area occupied by that capacity is lessened. This contributes to enlarging the numerical aperture of pixels.
The GOLD structure above is effective not only in enhancing the reliability of TFTs but also in suppressing leak currents through TFTs attributable to photoelectric currents. With the active matrix liquid crystal display apparatus, lighting coming from backlight devices is switched on and off by liquid crystal. On that apparatus, the TFTs are necessarily exposed to the backlight. A light beam hitting any TFT causes the internal photoelectric effect within a semiconductor layer to generate electron-hole pairs flowing as a current. What is worrying in particular is an increase of leak currents when the TFTs are turned off. The problem becomes pronounced with projection type display apparatuses because of high levels of light intensity involved. Photoelectric leak currents are known to appear particularly in high electrical field regions close to drains. The problem may be bypassed when the low-resistance semiconductor layer is formed in self-aligned relation to the second wiring, i.e., when the entire top surface of the high-resistance semiconductor layer subject to high electrical fields is covered with the second wiring. This arrangement prevents light from reaching the regions most prone to generate photoelectric currents, thereby implementing TFTs with small leak currents.
Preferably, ends of the second electrodes may be tapered by etching. This structure helps prevent disconnected staggers in staggered portions of the top-layer wiring.
Generally, it is difficult during the taper etching process to control pattern dimensions within a large-area substrate. In a single-drain structure in which gate electrodes form only a single layer, variations in the pattern dimensions translate unmitigated into variations of TFT gate lengths. This results in irregularly distributed current driving capabilities of the TFTs over the substrate, making uniform image displays difficult.
Since the TFT gate length is defined by the fabricated size of the first wiring, the tapering of the second wiring by anisotropic etching of high pattern accuracy makes it possible both to ease the staggered configuration and to control the gate length with high precision. Although tapering the second wiring necessarily entails its dimensional variations which add to variations in the overlapping length of the gates and high-resistance semiconductor layer, such variations in the second wiring dimensions are not associated with the gate length. Because variations in the overlapping length do not affect the current driving capability of the TFTs as much as variations in the gate length, the uniformity of TFT characteristics within the substrate surface is not adversely affected by the tapered formation.
The first wiring may be formed preferably by any one of elements Si, Nb, Ta, Mo, W, Al, Ti, Fe, Cr, V and Zr; or by an ally of Si or N and any one of Nb, Ta, Mo, W, Al, Ti, Fe, Cr, V and Zr. The second wiring may be formed preferably by any one of Nb, Ta, Mo, W, Al, Ti, Fe, Cr, V and Zr; or by an ally of Si or N and any one of Nb, Ta, Mo, W, Al, Ti, Fe, Cr, V and Zr. The first and the second wiring may both be made of the same material.
Other objects, features and advantages of the present invention will become more apparent in the following specification and accompanying drawings.